ʻO ka pā lawe lawe SiC no ke kāʻei LED

Ⅰ. Mea a me ka hoʻolālā hale

ʻO ke koho ʻenekinia a Semixlab o kahi substrate graphite isostatic maʻemaʻe kiʻekiʻe me ka uhi ʻana o ka CVD Sic mānoanoa a paʻakikī:

1. Hāʻawi ka graphite substrate i ka maikaʻi loa o ka lawe ʻana i ka wela, ke kaumaha kikoʻī haʻahaʻa, a me ke kūpaʻa maikaʻi loa i ka haʻalulu wela - e kōkua ana i ka hoʻohālikelike ʻana i ka wela ma waena o ka pā lawe i ka wā o ka pulsed a i ʻole ka lōʻihi etch cycles. Hoʻomaʻamaʻa ka Graphite i ka mīkini no nā hiʻohiʻona pololei a me ka huli ʻana i nā geometries.

2. ʻO ka uhi ʻana o ka CVD SiC he ʻili kemika inert, ʻaʻole hiki ke hoʻopili pololei me ka plasma a me ka wafer hope. Hoʻohālikelike ʻia me ka graphite ʻole, hoʻopau ka ʻili CVD SiC i nā wahi hana, hoʻemi i ka hoʻohaumia pili kalapona, a hoʻomaikaʻi nui i ke kūʻē ʻana i nā plasma halogen.

3. Ka hopena i hui pū ʻia: Mālama ka ʻōnaehana hybrid i nā pono wela a me ka machinability o ka graphite ʻoiai e hāʻawi ana i ka hoʻomalu contamination a me ka lōʻihi o ka ʻili o SiC.

Ⅱ. Nā Luʻi maʻamau a me nā hoʻonā Semixlab

1. Hoʻokumu ʻana i nā ʻāpana a me ka hoʻohaumia ʻana i ka ʻili

Hoʻoponopono: ʻO ka papa luna kiʻekiʻe CVD SiC + ka pau ʻana o ka nano-polish he nui (ʻano Ra ≤0.2 μm). Hana ʻia nā hoʻokolohua outgassing a me nā particulate ma mua o ka hoʻouna ʻana; nā laina pale koho no ka pale ʻana i ke ola.

2. ʻAi ʻia ka plasma o ka ʻili lawe

Solution: Optimized CVD SiC mānoanoa (customer-specified, typical 100-300 μm) a me ke koho TaC sealing layers in extreme chemistries.Accelerated plasma life testing (process recipe simulation) ma mua o ka hiki.

3. Coating delamination a i ʻole nā ​​hemahema o ka interface

Hoʻoponopono: ʻO nā hoʻomaʻamaʻa mua ʻana o ka ʻili (hoʻomaʻemaʻe+micro-texturing), nā mea hoʻopili paʻa i hoʻopaʻa ʻia, a me nā mea hoʻomaʻamaʻa haʻahaʻa haʻahaʻa e hōʻemi i ka like ʻole o ka wela a me ke koena o ke kaumaha.

4. ʻO ka hoʻoheheʻe wela a me ka warp i ka wā kaʻa kaʻa

Pane: ʻO ka geometry pāpaʻi hoʻoheheʻe ʻia e ka ʻeleʻele, ke koho ʻana i ka nui o ka substrate, a me ka hoʻopili ʻana ma hope o ka hana ʻana no ka hoʻopau ʻana i ke kaumaha.

Nā noi maʻamau i nā kaʻina hana Etch LED

Ma ke kaʻina hana etching LED, lawelawe ʻo SiC Carrier Plate ma ke ʻano he mechanical, thermal, a me kemika ma waena o ka wafer a me ke kaiapuni etching. ʻO Semixlab's SiC Carrier Plate, i kūkulu ʻia ma luna o kahi substrate graphite maʻemaʻe kiʻekiʻe me ka uhi ʻana o ka CVD SiC paʻa, i hana ʻia e hōʻoia i ka mālama ʻana i ka mahana wafer paʻa, ke kūpaʻa kemika, a me ka hana manuahi ʻole i nā pōʻai plasma mau. Aia ma lalo iho kahi wehewehe o kāna mau hiʻohiʻona noi nui i loko o nā laina etching LED:

1. Kākoʻo Wafer a me ka Hoʻokele Thermal ma ICP/RIE Etching

I loko o nā mea hana etching LED e like me SAMCO, Oxford Instruments, a me LAM ICP etchers, ua kau ʻia nā wafers (maʻamau 2-8 iniha, me GaN-on-Sapphire a i ʻole GaN-on-Si substrates) ma ka pā lawe lawe SiC.

Pono e hāʻawi ka mea lawe:

● Hoʻololi wela ma waena o ka wafer a me ka chuck electrostatic (ESC) a i ʻole ka hoʻopili mechanical;

● ʻO ka palahalaha maikaʻi loa e hōʻoia i ka hoʻolaha ʻana i ka plasma a me ka mana hohonu etch;

● Kiʻekiʻe thermal conductivity (i loaʻa mai ka graphite core) e hoopau localized overheating ("wela wahi wela") e hiki ke alakai i ka etch non-uniformity a i ole hoʻokumu hemahema.

Hāʻawi ka ʻōnaehana hybrid o Semixlab i kahi kiʻi wela paʻa (± 1°C ma ka ʻaoʻao o ka wafer), e ʻae i ka mana pololei o ka etch rate a me ke koho—koʻikoʻi no ka mālama ʻana i ka geometry LED mesa a me ka laumania ʻaoʻao.

2. ʻO ka hoʻokele wela ma hope a me ka pale Wafer

I loko o nā keʻena etch LED he nui, ua kau ʻia nā wafers ma ke alo i lalo, a hāʻawi ka ipu lawe i ka hoʻokele wela ma hope e mālama i ka like ʻana o ka mahana. ʻO nā mea liʻiliʻi liʻiliʻi ʻole i ka hoʻopili wela hiki ke alakaʻi i:

● Wehewehe ʻana i ka helu etch;

● Photoresist kuni;

● ʻAʻole kūlike ke kiʻekiʻe mesa—e hoʻohaʻahaʻa i nā hua LED.

ʻO kā Semixlab's mirror-finished CVD SiC coating e hōʻoiaʻiʻo ana i ka pilina wafer, aʻo ka graphite substrate e hoʻopaʻa i nā haʻalulu wela i ka wā o ka hoʻololi ʻana i ka meaʻai (e laʻa, ma waena o nā ʻanuʻu etch a me ka hoʻoluʻu).

Hoʻemi kēia hui ʻana i ke koʻikoʻi wafer a pale i nā microcracks i loko o nā substrates brittle sapphire a i ʻole GaN.

3. Mechanical Alignment a me Chamber Compatibility

Hoʻohana pū ʻia nā papa lawe ʻo SiC ma ke ʻano he mau pilina mechanical pololei ma waena o ka wafer a me ka lako keena kaʻina hana.

ʻO ke ʻano māmā a me ka machinable o ka graphite core e hiki ai i nā geometries paʻakikī-e like me nā lua alignment, recesses, a me nā ʻaoʻao hope-e ʻae i ka hoʻohui pono ʻana me nā hoʻonohonoho hāmeʻa like ʻole.

Hōʻoia ka hoʻolālā o Semixlab:

● Hoʻohālikelike ʻia me nā etchers pūʻulu wafer nui a me nā mea hana wafer hoʻokahi;

● maʻalahi ka wafer hoʻouka / wehe ʻana me nā lima robotic;

● Hoʻemi ʻia ke koʻikoʻi mechanical ma nā wafers GaN palupalu i ka wā o ka hoʻololi ʻana.